1. Technical Field
The present invention relates to a test apparatus and a domain synchronization method.
2. Related Art
Patent Document 1, for example, discloses a test apparatus comprising a reference clock generating section that generates a reference clock having a first frequency, a first test rate generating section that generates a first test rate clock having a frequency that is substantially an integer multiple of the first frequency, a second test rate generating section that generates a second test rate clock having a frequency that is different from the frequency of the first test rate clock, a first driver that supplies an electronic device with a test pattern according to the first test rate clock, and a second driver that supplies the electronic device with a test pattern according to the second test rate clock. Patent Document 1 further discloses that the domains are synchronized with each other at a start time in the test apparatus.    Patent Document 1: International Publication WO 2003/062843
The test apparatus can achieve synchronization between domains at a start time. However, in order to achieve synchronization of the domains during operation, there is a prescribed limitation. Specifically, a timing must be found that is a common multiple of the phases of the operational clock and the period signal, and synchronization must be achieved at the timing that is a common multiple of the phases of the operational clock and period signal of each domain that is to be synchronized. This requirement imposes a limitation when creating the pattern program, and makes creation of the pattern program more complicated. Accordingly, a synchronization method is desired that does not impose many restrictions on the pattern program creation.